1990 search results - page 8 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
ICCD
1999
IEEE
13 years 11 months ago
1999
IEEE
We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a...
IEEEPACT
1999
IEEE
13 years 11 months ago
1999
IEEE
Trace cache, an instruction fetch technique that reduces taken branch penalties by storing and fetching program instructions in dynamic execution order, dramatically improves inst...
MICRO
2003
IEEE
14 years 23 days ago
2003
IEEE
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...
DATE
2011
IEEE
12 years 11 months ago
2011
IEEE
Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case...