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CODES
2008
IEEE
14 years 3 months ago
Speculative DMA for architecturally visible storage in instruction set extensions
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Ch...
TJS
2002
83views more  TJS 2002»
13 years 8 months ago
An I/O-Conscious Tiling Strategy for Disk-Resident Data Sets
This paper describes a tiling technique that can be used by application programmers and optimizing compilers to obtain I/O-efficient versions of regular scientific loop nests. Due ...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
EUROSYS
2007
ACM
14 years 5 months ago
Removing the memory limitations of sensor networks with flash-based virtual memory
Virtual memory has been successfully used in different domains to extend the amount of memory available to applications. We have adapted this mechanism to sensor networks, where,...
Andreas Lachenmann, Pedro José Marró...
ISPASS
2010
IEEE
14 years 3 months ago
Visualizing complex dynamics in many-core accelerator architectures
—While many-core accelerator architectures, such as today’s Graphics Processing Units (GPUs), offer orders of magnitude more raw computing power than contemporary CPUs, their m...
Aaron Ariel, Wilson W. L. Fung, Andrew E. Turner, ...
ICCAD
1995
IEEE
144views Hardware» more  ICCAD 1995»
14 years 4 days ago
Background memory management for dynamic data structure intensive processing systems
Abstract -- Telecommunication network management applications often require application-specific ICs that use large dynamically allocated stored data structures. Currently availab...
Gjalt G. de Jong, Bill Lin, Carl Verdonck, Sven Wu...