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ISPD
2004
ACM
150views Hardware» more  ISPD 2004»
14 years 1 months ago
Topology optimization of structured power/ground networks
This paper presents an efficient method for optimizing the design of power/ground (P/G) networks by using locally regular, globally irregular grids. The procedure divides the pow...
Jaskirat Singh, Sachin S. Sapatnekar
VLSID
2002
IEEE
100views VLSI» more  VLSID 2002»
14 years 16 days ago
Layout-Driven Timing Optimization by Generalized De Morgan Transform
We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. ...
Supratik Chakraborty, Rajeev Murgai
VLSID
1999
IEEE
104views VLSI» more  VLSID 1999»
13 years 12 months ago
Interconnect Optimization Strategies for High-Performance VLSI Designs
Interconnect tuning and repeater insertion are necessary to optimize interconnectdelay, signalperformanceandintegrity, andinterconnectmanufacturability and reliability. Repeater i...
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
DATE
2006
IEEE
87views Hardware» more  DATE 2006»
14 years 1 months ago
Thermal resilient bounded-skew clock tree optimization methodology
The existence of non-uniform thermal gradients on the substrate in high performance IC’s can significantly impact the performance of global on-chip interconnects. This issue is...
Ashutosh Chakraborty, Prassanna Sithambaram, Karth...
ISVC
2005
Springer
14 years 1 months ago
A Vectorial Self-dual Morphological Filter Based on Total Variation Minimization
We present a vectorial self dual morphological filter. Contrary to many methods, our approach does not require the use of an ordering on vectors. It relies on the minimization of ...
Jérôme Darbon, Sylvain Peyronnet