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PADS
2009
ACM
14 years 2 months ago
Scalable Time Warp on Blue Gene Supercomputers
Abstract—In this paper we illustrate scalable parallel performance for the Time Warp synchronization protocol on the L and P variants of the IBM Blue Gene supercomputer. Scalable...
David W. Bauer, Christopher D. Carothers, Akintayo...
MTV
2007
IEEE
121views Hardware» more  MTV 2007»
14 years 1 months ago
Chico: An On-chip Hardware Checker for Pipeline Control Logic
The widening gap between CPU complexity and verification capability is becoming increasingly more salient. It is impossible to completely verify the functionality of a modern mic...
Andrew DeOrio, Adam Bauserman, Valeria Bertacco
ICCD
2003
IEEE
121views Hardware» more  ICCD 2003»
14 years 4 months ago
Distributed Reorder Buffer Schemes for Low Power
We consider several approaches for reducing the complexity and power dissipation in processors that use separate register file to maintain the commited register values. The first ...
Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad ...
DAC
2006
ACM
14 years 8 months ago
Shielding against design flaws with field repairable control logic
Correctness is a paramount attribute of any microprocessor design; however, without novel technologies to tame the increasing complexity of design verification, the amount of bugs...
Ilya Wagner, Valeria Bertacco, Todd M. Austin
IEEEPACT
2007
IEEE
14 years 1 months ago
Error Detection Using Dynamic Dataflow Verification
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...
Albert Meixner, Daniel J. Sorin