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GLOBECOM
2006
IEEE
14 years 1 months ago
Investigation of Error Floors of Structured Low-Density Parity-Check Codes by Hardware Emulation
Abstract−Several high performance LDPC codes have paritycheck matrices composed of permutation submatrices. We design a parallel-serial architecture to map the decoder of any str...
Zhengya Zhang, Lara Dolecek, Borivoje Nikolic, Ven...
ICASSP
2008
IEEE
14 years 1 months ago
Design of block-structured LDPC codes for iterative receivers with soft sphere detection
In this paper we design block-structured LDPC codes for iterative MIMO receivers with soft sphere detection in particular channel environments. The receiver EXIT charts are used a...
Predrag Radosavljevic, Joseph R. Cavallaro
TIT
2010
140views Education» more  TIT 2010»
13 years 2 months ago
Iterative decoding threshold analysis for LDPC convolutional codes
Abstract--An iterative decoding threshold analysis for terminated regular LDPC convolutional (LDPCC) codes is presented. Using density evolution techniques, the convergence behavio...
Michael Lentmaier, Arvind Sridharan, Daniel J. Cos...
DATE
2009
IEEE
144views Hardware» more  DATE 2009»
14 years 2 months ago
Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing
—FPGAs are widely used for evaluating the error-floor performance of LDPC (low-density parity check) codes. We propose a scalable vector decoder for FPGA-based implementation of...
Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Ake...
ISCAS
2007
IEEE
141views Hardware» more  ISCAS 2007»
14 years 1 months ago
Towards a GBit/s Programmable Decoder for LDPC Convolutional Codes
Abstract— We analyze the decoding algorithm for regular timeinvariant LDPC convolutional codes as a 3D signal processing scheme and derive several parallelization concepts, which...
Emil Matús, Marcos B. S. Tavares, Marcel Bi...