339 search results - page 21 / 68 » Overview on Low Power SoC Design Technology |
VLSID
2008
IEEE
14 years 2 months ago
2008
IEEE
With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of poweraware design methodologies have resulted in potentially significa...
ICIP
2003
IEEE
14 years 9 months ago
2003
IEEE
For motion estimation (ME) and discrete cosine transform (DCT) of MPEG video encoding, content variation and perceptual tolerance in video signals can be exploited to gracefully t...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
ECCTD
2011
12 years 7 months ago
2011
⎯ Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate th...
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...