339 search results - page 42 / 68 » Overview on Low Power SoC Design Technology |
TC
2008
13 years 7 months ago
2008
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
CODES
2011
IEEE
12 years 7 months ago
2011
IEEE
Designing memory controllers for complex real-time and highperformance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must b...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract—Design guidelines for resonant H-tree clock distribution networks are presented in this paper. A distributed model of a two-level resonant H-tree structure is described,...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
The prospective use of upcoming nanometer CMOS technology nodes (65nm, 45nm, and beyond) in bioelectronic interfaces is raising a number of important issues concerning circuit arc...
GI
2004
Springer
14 years 27 days ago
2004
Springer
: Next to authentication, secure key exchange is considered the most critical and complex issue regarding ad-hoc network security. We present a low-cost, (i.e. low hardware-complex...