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» Overview on Low Power SoC Design Technology
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ISQED
2009
IEEE
86views Hardware» more  ISQED 2009»
14 years 2 months ago
Uncriticality-directed scheduling for tackling variation and power challenges
The advance in semiconductor technologies presents the serious problem of parameter variations. They affect threshold voltage of transistors and thus circuit delay has variability...
Toshinori Sato, Shingo Watanabe
ISCAS
2007
IEEE
79views Hardware» more  ISCAS 2007»
14 years 1 months ago
Impact of strain on the design of low-power high-speed circuits
- In this article, we explore the impact of strain on circuit performance when strained silicon (s-Si) devices are used for designing low-power high-speed circuits. Emphasis has be...
H. Ramakrishnan, K. Maharatna, S. Chattopadhyay, A...
ICMCS
2006
IEEE
154views Multimedia» more  ICMCS 2006»
14 years 1 months ago
Design of Audio and Video decoder for the T-DMB Receiver
We present a low-power architectural MPEG-4 part-10 AVC/H.264 video and MPEG-4 BSAC audio decoder chip capable of delivering high-quality and high-compression in wireless multimed...
Bontae Koo, Juhyun Lee, Sekho Lee, Jinkyu Kim, Min...
JCM
2007
126views more  JCM 2007»
13 years 7 months ago
Design Concepts and First Implementations for 24 GHz Wireless Sensor Nodes
— This paper reviews proposed realization concepts and achievements of wireless sensor nodes and focuses on new developments in the 24 GHz frequency range. The relatively high fr...
Stefan von der Mark, Meik Huber, Georg Boeck
DSD
2007
IEEE
160views Hardware» more  DSD 2007»
14 years 1 months ago
Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
Scott Miller, Mihai Sima, Michael McGuire