339 search results - page 50 / 68 » Overview on Low Power SoC Design Technology |
CCECE
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper describes a model and a setup for emulating fractal and multifractal noise for the measurement and evaluation of performance of ZigBee mesh networks intended for harsh ...
SLIP
2009
ACM
14 years 2 months ago
2009
ACM
Different interconnection structures have been proposed to solve the performance limitation caused by scaling of on-chip global wires. In this paper, we give an overview of curre...
GLVLSI
2010
IEEE
14 years 7 days ago
2010
IEEE
Graphene nanoribbon tunneling FETs (GNR TFETs) are promising devices for post-CMOS low-power applications because of the low subthreshold swing, high Ion/Ioff, and potential for l...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...