339 search results - page 56 / 68 » Overview on Low Power SoC Design Technology |
GLVLSI
2003
IEEE
14 years 23 days ago
2003
IEEE
In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 2...
JCP
2008
13 years 7 months ago
2008
Semiconductor manufacturing process scaling increases leakage and transistor variations, both of which are problematic for static random access memory (SRAM). Since SRAM is a criti...
ISLPED
2009
ACM
14 years 2 months ago
2009
ACM
In this paper, we observe that minimum energy Emin of subthreshold logic dramatically increases when reaching 45 nm node. We demonstrate by circuit simulation and analytical model...
DAC
2006
ACM
14 years 1 months ago
2006
ACM
duce system weight and volume, increase operating lifetime, The recent explosion in capability of embedded and portable decrease maintenance costs, and open new frontiers for inele...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...