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» PAPER - Accelerating parallel evaluations of ROCS
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HPCC
2009
Springer
15 years 8 months ago
Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory
Abstract--Transactional Memory (TM) is an emerging technology which promises to make parallel programming easier. However, to be efficient, underlying TM system should protect only...
Sutirtha Sanyal, Sourav Roy, Adrián Cristal...
CLUSTER
2008
IEEE
15 years 6 months ago
Efficient one-copy MPI shared memory communication in Virtual Machines
Efficient intra-node shared memory communication is important for High Performance Computing (HPC), especially with the emergence of multi-core architectures. As clusters continue ...
Wei Huang, Matthew J. Koop, Dhabaleswar K. Panda
EUROPAR
2010
Springer
15 years 4 months ago
Optimized On-Chip-Pipelined Mergesort on the Cell/B.E
Abstract. Limited bandwidth to off-chip main memory is a performance bottleneck in chip multiprocessors for streaming computations, such as Cell/B.E., and this will become even mor...
Rikard Hultén, Christoph W. Kessler, Jö...
ISCA
2007
IEEE
94views Hardware» more  ISCA 2007»
15 years 4 months ago
Tailoring quantum architectures to implementation style: a quantum computer for mobile and persistent qubits
In recent years, quantum computing (QC) research has moved from the realm of theoretical physics and mathematics into real implementations [9]. With many different potential hardw...
Eric Chi, Stephen A. Lyon, Margaret Martonosi
IPPS
2010
IEEE
15 years 2 months ago
Supporting fault tolerance in a data-intensive computing middleware
Over the last 2-3 years, the importance of data-intensive computing has increasingly been recognized, closely coupled with the emergence and popularity of map-reduce for developin...
Tekin Bicer, Wei Jiang, Gagan Agrawal