13 search results - page 3 / 3 » PMOS breakdown effects on digital circuits - Modeling and an... |
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper proposes an innovative methodology to perform and validate a Failure Mode and Effects Analysis (FMEA) at System-on-Chip (SoC) level. This is done in compliance with the...
GLVLSI
2009
IEEE
13 years 10 months ago
2009
IEEE
Mounting concerns over variability, defects and noise motivate a new approach for integrated circuits: the design of stochastic logic, that is to say, digital circuitry that opera...
TC
2011
13 years 1 months ago
2011
—Mounting concerns over variability, defects and noise motivate a new approach for digital circuitry: stochastic logic, that is to say, logic that operates on probabilistic signa...