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DATE
2007
IEEE
106views Hardware» more  DATE 2007»
14 years 1 months ago
Low-cost protection for SER upsets and silicon defects
Extreme transistor scaling trends in silicon technology are soon to reach a point where manufactured systems will suffer from limited device reliability and severely reduced life...
Mojtaba Mehrara, Mona Attariyan, Smitha Shyam, Kyp...
ISCA
2007
IEEE
114views Hardware» more  ISCA 2007»
14 years 1 months ago
Mechanisms for bounding vulnerabilities of processor structures
Concern for the increasing susceptibility of processor structures to transient errors has led to several recent research efforts that propose architectural techniques to enhance r...
Niranjan Soundararajan, Angshuman Parashar, Anand ...
IISWC
2006
IEEE
14 years 1 months ago
Performance Cloning: A Technique for Disseminating Proprietary Applications as Benchmarks
Many embedded real world applications are intellectual property, and vendors hesitate to share these proprietary applications with computer architects and designers. This poses a ...
Ajay Joshi, Lieven Eeckhout, Robert H. Bell Jr., L...
ISPASS
2006
IEEE
14 years 1 months ago
Comparing simulation techniques for microarchitecture-aware floorplanning
— Due to the long simulation times of the reference input sets, microarchitects resort to alternative techniques to speed up cycle-accurate simulations. However, the reduction in...
Vidyasagar Nookala, Ying Chen, David J. Lilja, Sac...
MICRO
2006
IEEE
155views Hardware» more  MICRO 2006»
14 years 1 months ago
In-Network Cache Coherence
With the trend towards increasing number of processor cores in future chip architectures, scalable directory-based protocols for maintaining cache coherence will be needed. Howeve...
Noel Eisley, Li-Shiuan Peh, Li Shang