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ISSS
2002
IEEE
154views Hardware» more  ISSS 2002»
14 years 13 days ago
Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops
Software pipelining and unfolding are commonly used techniques to increase parallelism for DSP applications. However, these techniques expand the code size of the application sign...
Bin Xiao, Zili Shao, Chantana Chantrapornchai, Edw...
IISWC
2006
IEEE
14 years 1 months ago
Modeling Cache Sharing on Chip Multiprocessor Architectures
— As CMPs are emerging as the dominant architecture for a wide range of platforms (from embedded systems and game consoles, to PCs, and to servers) the need to manage on-chip res...
Pavlos Petoumenos, Georgios Keramidas, Håkan...
DAC
2012
ACM
11 years 10 months ago
WCET-centric partial instruction cache locking
Caches play an important role in embedded systems by bridging the performance gap between high speed processors and slow memory. At the same time, caches introduce imprecision in ...
Huping Ding, Yun Liang, Tulika Mitra
CASES
2004
ACM
13 years 11 months ago
Reducing energy consumption of queries in memory-resident database systems
The tremendous growth of system memories has increased the capacities and capabilities of memory-resident embedded databases, yet current embedded databases need to be tuned in or...
Jayaprakash Pisharath, Alok N. Choudhary, Mahmut T...
DATE
2007
IEEE
89views Hardware» more  DATE 2007»
14 years 1 months ago
Mapping multi-dimensional signals into hierarchical memory organizations
The storage requirements of the array-dominated and looporganized algorithmic specifications running on embedded systems can be significant. Employing a data memory space much l...
Hongwei Zhu, Ilie I. Luican, Florin Balasa