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» PVS: A Prototype Verification System
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EURODAC
1994
IEEE
122views VHDL» more  EURODAC 1994»
13 years 11 months ago
Compiled-code-based simulation with timing verification
Due to the complexity of today's systems, prototyping by simulation must be based on simulation-engine-like performance. It is proved by implementations that compiler-driven ...
Winfried Hahn, Andreas Hagerer, C. Herrmann
FDL
2005
IEEE
14 years 1 months ago
PSL-based online monitoring of digital systems
We present an original method for generating monitors that capture the occurrence of events, specified by logical and temporal properties under the form of assertions in declarati...
D. Borionne, M. Liu, P. Ostier, Laurent Fesquet
DAC
2002
ACM
14 years 8 months ago
High-Level specification and automatic generation of IP interface monitors
A central problem in functional verification is to check that a circuit block is producing correct outputs while enforcing that the environment is providing legal inputs. To attac...
Marcio T. Oliveira, Alan J. Hu
FPL
2009
Springer
107views Hardware» more  FPL 2009»
14 years 4 days ago
An FPGA based verification platform for HyperTransport 3.x
In this paper we present a verification platform designed for HyperTransport 3.x (HT3) applications. HyperTransport 3.x is a very low latency and high bandwidth chip-tochip interc...
Heiner Litz, Holger Fröning, Maximilian Th&uu...
CCECE
2006
IEEE
14 years 1 months ago
A Formal CSP Framework for Message-Passing HPC Programming
To help programmers of high-performance computing (HPC) systems avoid communication-related errors, we employ a formal process algebra, Communicating Sequential Processes (CSP), w...
John D. Carter, William B. Gardner