145 search results - page 3 / 29 » Parallel Global Routing Algorithms for Standard Cells |
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper, we present an experimental integrated platform for the research, development and evaluation of new VLSI back-end algorithms and design flows. Interconnect scaling ...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
Global routing is an important step in the physical design process. In this paper, we propose a new global routing algorithm Archer, which resolves some of the most common problem...
ICCD
1997
IEEE
13 years 11 months ago
1997
IEEE
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
ICCAD
1990
IEEE
13 years 11 months ago
1990
IEEE
We present a hierarchicaltechniquefor floorplanning and pin assignment of the general cell layouts. Given a set of cells with their shape lists, a layout aspect ratio, relative po...
EUROPAR
2007
Springer
14 years 1 months ago
2007
Springer
We present in detail a GCA (Global Cellular Automaton) algorithm with 3n cells for Hirschberg’s algorithm which determines the connected components of a n-node undirected graph w...