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CODES
2005
IEEE
14 years 1 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
PPOPP
2009
ACM
14 years 8 months ago
Efficient and scalable multiprocessor fair scheduling using distributed weighted round-robin
Fairness is an essential requirement of any operating system scheduler. Unfortunately, existing fair scheduling algorithms are either inaccurate or inefficient and non-scalable fo...
Tong Li, Dan P. Baumberger, Scott Hahn
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
14 years 1 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
HPDC
2009
IEEE
14 years 2 months ago
Resource co-allocation for large-scale distributed environments
Advances in the development of large scale distributed computing systems such as Grids and Computing Clouds have intensified the need for developing scheduling algorithms capable...
Claris Castillo, George N. Rouskas, Khaled Harfous...
ASPLOS
2000
ACM
13 years 12 months ago
Architectural Support for Fast Symmetric-Key Cryptography
The emergence of the Internet as a trusted medium for commerce and communication has made cryptography an essential component of modern information systems. Cryptography provides ...
Jerome Burke, John McDonald, Todd M. Austin