88 search results - page 12 / 18 » Parallel Logic Simulation of VLSI Systems |
ICPP
2007
IEEE
14 years 2 months ago
2007
IEEE
A self-organizing peer-to-peer system is built upon an application level overlay, whose topology is independent of underlying physical network. A well-routed message path in such ...
IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
We propose a novel design estimation method for adaptive streaming applications to be implemented on a partially reconfigurable FPGA. Based on experimental results we enable accu...
AADEBUG
2005
Springer
14 years 1 months ago
2005
Springer
Reprogrammable hardware systems are traditionally very difficult to debug due to their high level of parallelism. In our solution to this problem, features are inserted into the u...
FCCM
2003
IEEE
14 years 1 months ago
2003
IEEE
Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation- or PC-based simulation. We describe a hardwar...
DFT
2003
IEEE
14 years 1 months ago
2003
IEEE
The implementation of imaging arrays for System-On-a-Chip (SOC) is aided by using faulttolerant light sensors. Fault-tolerant redundancy in an Active Pixel Sensor (APS) is obtaine...