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» Parallel Logic Simulation of VLSI Systems
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DATE
1997
IEEE
107views Hardware» more  DATE 1997»
14 years 7 days ago
Acceleration of behavioral simulation on simulation specific machines
Behavioral simulation is faster than gate-level logic simulation, however, the simulation speed is too slow for large systems. Simulation specific machines accelerated simulation ...
Minoru Shoji, Fumiyasu Hirose, Shintaro Shimogori,...
TVLSI
2002
130views more  TVLSI 2002»
13 years 7 months ago
Incremental compilation for parallel logic verification systems
Although simulation remains an important part of application-specific integrated circuit (ASIC) validation, hardware-assisted parallel verification is becoming a larger part of the...
R. Tessier, S. Jana
ANSS
2000
IEEE
14 years 13 days ago
An Analytic Method for Predicting Simulation Parallelism
The abilityto predict the performance of a simulationapplicationbefore its implementationis an important factor to the adoption of parallel simulation technology in industry. Idea...
Hong Wang, Yong Meng Teo, Seng Chuan Tay
SBCCI
2003
ACM
135views VLSI» more  SBCCI 2003»
14 years 1 months ago
Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic
The growing adoption of reconfigurable architectures opens new implementation alternatives and creates new design challenges. In the case of dynamically reconfigurable architectur...
Mauricio Ayala-Rincón, Rodrigo B. Nogueira,...
DATE
2000
IEEE
140views Hardware» more  DATE 2000»
14 years 13 days ago
Parallel and Distributed VHDL Simulation
This paper presents a methodology for parallel and distributed simulation of VHDL using the PDES (parallel discrete-event simulation) paradigm. To achieve better features and perf...
Dragos Lungeanu, C.-J. Richard Shi