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» Parallel Logic Simulation of VLSI Systems
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DAC
2004
ACM
13 years 11 months ago
Communication-efficient hardware acceleration for fast functional simulation
This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more tim...
Young-Il Kim, Woo-Seung Yang, Young-Su Kwon, Chong...
ICDCS
2008
IEEE
14 years 2 months ago
Scalable and Adaptive Metadata Management in Ultra Large-Scale File Systems
This paper presents a scalable and adaptive decentralized metadata lookup scheme for ultra large-scale file systems (≥ Petabytes or even Exabytes). Our scheme logically organiz...
Yu Hua, Yifeng Zhu, Hong Jiang, Dan Feng, Lei Tian
WSC
1997
13 years 9 months ago
Java Based Conservative Distributed Simulation
Distributed discrete event simulation techniques aim at an acceleration of the execution of a self-contained simulation model by the spatial decomposition of that model and the co...
Alois Ferscha, Michael Richter
ASYNC
2003
IEEE
86views Hardware» more  ASYNC 2003»
14 years 1 months ago
A High-Speed Clockless Serial Link Transceiver
We present a high-speed, clockless, serial link transceiver for inter-chip communication in asynchronous VLSI systems. Serial link transceivers achieve high offchip data rates by ...
John Teifel, Rajit Manohar
TCAD
2002
146views more  TCAD 2002»
13 years 7 months ago
Static scheduling of multidomain circuits for fast functional verification
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
Murali Kudlugi, Russell Tessier