309 search results - page 26 / 62 » Parallel Memory Architecture for Arbitrary Stride Accesses |
HPCA
2007
IEEE
14 years 8 months ago
2007
IEEE
This paper presents hardware and software mechanisms to enable concurrent direct network access (CDNA) by operating systems running within a virtual machine monitor. In a conventi...
CODES
2001
IEEE
13 years 11 months ago
2001
IEEE
Most research to date on energy minimization in DSP processors has focuses on hardware solution. This paper examines the software-based factors affecting performance and energy co...
EUROPAR
2009
Springer
14 years 5 days ago
2009
Springer
In response to the constant increase in wire delays, Non-Uniform Cache Architecture (NUCA) has been introduced as an effective memory model for dealing with growing memory latenci...
IPPS
1997
IEEE
13 years 11 months ago
1997
IEEE
We present the Data Parallel Fortran (DPF) benchmark suite, a set of data parallel Fortran codes forevaluatingdata parallel compilers appropriatefor any target parallel architectu...
IEEEPACT
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Load elimination is a classical compiler transformation that is increasing in importance for multi-core and many-core architectures. The effect of the transformation is ...