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ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
13 years 11 months ago
Performance Comparison of ILP Machines with Cycle Time Evaluation
Many studies have investigated performance improvement through exploiting instruction-level parallelism (ILP) with a particular architecture. Unfortunately, these studies indicate...
Tetsuya Hara, Hideki Ando, Chikako Nakanishi, Masa...
SIGGRAPH
1994
ACM
13 years 11 months ago
Fast volume rendering using a shear-warp factorization of the viewing transformation
Several existing volume rendering algorithms operate by factoring the viewing transformation into a 3D shear parallel to the data slices, a projection to form an intermediate but ...
Philippe Lacroute, Marc Levoy
DAC
2010
ACM
13 years 11 months ago
Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms
We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system...
Chenjie Yu, Peter Petrov
CASES
2006
ACM
13 years 11 months ago
Reaching fast code faster: using modeling for efficient software thread integration on a VLIW DSP
When integrating software threads together to boost performance on a processor with instruction-level parallel processing support, it is rarely clear which code regions should be ...
Won So, Alexander G. Dean
ISCA
1995
IEEE
92views Hardware» more  ISCA 1995»
13 years 11 months ago
A Comparison of Full and Partial Predicated Execution Support for ILP Processors
One can e ectively utilize predicated execution to improve branch handling in instruction-level parallel processors. Although the potential bene ts of predicated execution are hig...
Scott A. Mahlke, Richard E. Hank, James E. McCormi...