833 search results - page 128 / 167 » Parallel Processing Architectures for Reconfigurable Systems |
ASAP
2003
IEEE
14 years 1 months ago
2003
IEEE
On-chip implementation of multiprocessor systems requires the planarization of the interconnect network onto the silicon floorplan. Manual floorplanning approaches will become i...
CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
We present design technology for the structured design and programming of embedded multi-processor systems. It comprises a task-level interface that can be used both for developin...
PODC
1995
ACM
13 years 11 months ago
1995
ACM
The Horus system supports a communication architecture ats protocols as instances of an abstract data type. This approach encourages developers to partition complex protocols into...
PADL
2007
Springer
14 years 1 months ago
2007
Springer
Abstract. We describe a declarative language, called BAD (brain architecture description language), which we have developed for describing and then running brain models. Models are...
IISWC
2009
IEEE
14 years 2 months ago
2009
IEEE
—This paper presents and characterizes Rodinia, a benchmark suite for heterogeneous computing. To help architects study emerging platforms such as GPUs (Graphics Processing Units...