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» Parallel Processing Architectures for Reconfigurable Systems
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HPCA
2006
IEEE
14 years 8 months ago
BulletProof: a defect-tolerant CMP switch architecture
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
Kypros Constantinides, Stephen Plaza, Jason A. Blo...
USENIX
2008
13 years 10 months ago
A Comparative Experimental Study of Parallel File Systems for Large-Scale Data Processing
Large-scale scientific and business applications require data processing of ever-increasing amounts of data, fueling a demand for scalable parallel file systems comprising hundred...
Zoe Sebepou, Kostas Magoutis, Manolis Marazakis, A...
DATE
2008
IEEE
153views Hardware» more  DATE 2008»
14 years 2 months ago
An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications
Novel reconfigurable computing platforms enable efficient realizations of complex signal processing applications by allowing exploitation of parallelization resulting in high thro...
Sankalita Saha, Jason Schlessman, Sebastian Puthen...
KBSE
2010
IEEE
13 years 6 months ago
RESISTing reliability degradation through proactive reconfiguration
Situated software systems are an emerging class of systems that are predominantly pervasive, embedded, and mobile. They are marked with a high degree of unpredictability and dynam...
Deshan Cooray, Sam Malek, Roshanak Roshandel, Davi...
DATE
2009
IEEE
242views Hardware» more  DATE 2009»
14 years 2 months ago
A high performance reconfigurable Motion Estimation hardware architecture
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. For the recently available high definition frame sizes and hi...
Ozgur Tasdizen, Halil Kukner, Abdulkadir Akin, Ilk...