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» Parallel Programming with Transactional Memory
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ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
14 years 27 days ago
Piranha: a scalable architecture based on single-chip multiprocessing
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
Luiz André Barroso, Kourosh Gharachorloo, R...
EUROPAR
1999
Springer
14 years 24 days ago
I/O-Conscious Tiling for Disk-Resident Data Sets
This paper describes a tiling technique that can be used by application programmers and optimizing compilers to obtain I/O-efficient versions of regular scientific loop nests. Du...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
IPPS
2006
IEEE
14 years 2 months ago
Securing embedded programmable gate arrays in secure circuits
The purpose of this article is to propose a survey of possible approaches for implementing embedded reconfigurable gate arrays into secure circuits. A standard secure interfacing ...
Nicolas Valette, Lionel Torres, Gilles Sassatelli,...
HPCA
1998
IEEE
14 years 23 days ago
Using Multicast and Multithreading to Reduce Communication in Software DSM Systems
This paper examines the performance benefits of employing multicast communication and application-level multithreading in the Brazos software distributed shared memory (DSM) syste...
Evan Speight, John K. Bennett
HPCN
1994
Springer
14 years 18 days ago
Experiments with HPF Compilation for a Network of Workstations
Abstract. High Performance Fortran (hpf) is a data-parallel Fortran for Distributed Memory Multiprocessors. Hpf provides an interesting programming model but compilers are yet to c...
Fabien Coelho