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» Parallel Programming with Transactional Memory
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ISLPED
2005
ACM
93views Hardware» more  ISLPED 2005»
14 years 2 months ago
Power-aware code scheduling for clusters of active disks
In this paper, we take the idea of application-level processing on disks to one level further, and focus on an architecture, called Cluster of Active Disks (CAD), where the storag...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir
HPCA
2008
IEEE
14 years 8 months ago
Automated microprocessor stressmark generation
Estimating the maximum power and thermal characteristics of a processor is essential for designing its power delivery system, packaging, cooling, and power/thermal management sche...
Ajay M. Joshi, Lieven Eeckhout, Lizy Kurian John, ...
TPHOL
2009
IEEE
14 years 3 months ago
A Formalisation of Smallfoot in HOL
In this paper a general framework for separation logic inside the HOL theorem prover is presented. This framework is based on Abeparation Logic. It contains a model of an abstract,...
Thomas Tuerk
CASES
2007
ACM
14 years 12 days ago
Hierarchical coarse-grained stream compilation for software defined radio
Software Defined Radio (SDR) is an emerging embedded domain where the physical layer of wireless protocols is implemented in software rather than the traditional application speci...
Yuan Lin, Manjunath Kudlur, Scott A. Mahlke, Trevo...
ICS
2004
Tsinghua U.
14 years 1 months ago
Inter-reference gap distribution replacement: an improved replacement algorithm for set-associative caches
We propose a novel replacement algorithm, called InterReference Gap Distribution Replacement (IGDR), for setassociative secondary caches of processors. IGDR attaches a weight to e...
Masamichi Takagi, Kei Hiraki