1075 search results - page 213 / 215 » Parallel Programming with Transactional Memory |
CANPC
1999
Springer
14 years 20 days ago
1999
Springer
Streamlining communication is key to achieving good performance in shared-memory parallel programs. While full hardware support for cache coherence generally offers the best perfo...
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
Hard-to-predict branches depending on longlatency cache-misses have been recognized as a major performance obstacle for modern microprocessors. With the widening speed gap between...
ASPLOS
2006
ACM
14 years 2 months ago
2006
ACM
The sustained push toward smaller and smaller technology sizes has reached a point where device reliability has moved to the forefront of concerns for next-generation designs. Sil...
ICS
2005
Tsinghua U.
14 years 1 months ago
2005
Tsinghua U.
In an out-of-order issue processor, instructions are dynamically reordered and issued to function units in their dataready order rather than their original program order to achiev...
ASPLOS
2004
ACM
14 years 1 months ago
2004
ACM
Maintenance is the dominant source of downtime at high availability sites. Unfortunately, the dominant mechanism for reducing this downtime, cluster rolling upgrade, has two short...