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» Parallel Programming with Transactional Memory
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ASPLOS
2011
ACM
13 years 1 months ago
Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory
Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such a...
Luke Dalessandro, François Carouge, Sean Wh...
MICRO
2010
IEEE
242views Hardware» more  MICRO 2010»
13 years 7 months ago
ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory
Advanced Synchronization Facility (ASF) is an AMD64 hardware extension for lock-free data structures and transactional memory. It provides a speculative region that atomically exec...
Jae-Woong Chung, Luke Yen, Stephan Diestelhorst, M...
IEEEPACT
2009
IEEE
14 years 4 months ago
Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading
— This research demonstrates that coming support for hardware transactional memory can be leveraged to significantly reduce the cost of implementing true speculative multithread...
Leo Porter, Bumyong Choi, Dean M. Tullsen
POPL
2008
ACM
14 years 10 months ago
Semantics of transactional memory and automatic mutual exclusion
Software Transactional Memory (STM) is an attractive basis for the development of language features for concurrent programming. However, the semantics of these features can be del...
Andrew Birrell, Martín Abadi, Michael Isard...
ICA3PP
2009
Springer
14 years 2 months ago
A Software Transactional Memory Service for Grids
In-memory data sharing for grids allow location-transparent access to data stored in volatile memory. Existing Grid middlewares typ- ically support only explicit data transfer betw...
Kim-Thomas Möller, Marc-Florian Müller, ...