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ISQED
2008
IEEE
154views Hardware» more  ISQED 2008»
14 years 1 months ago
Error Protected Data Bus Inversion Using Standard DRAM Components
Off-chip communication consumes a significant part of main memory system power. Existing solutions imply the use of specialized memories or assume error free environments. This i...
Maurizio Skerlj, Paolo Ienne
VLSISP
2010
119views more  VLSISP 2010»
13 years 1 months ago
Hardware Acceleration of HMMER on FPGAs
We propose a new parallelization scheme for the hmmsearch function of the HMMER software, in order to target FPGA technology. hmmsearch is a very compute intensive software for bio...
Steven Derrien, Patrice Quinton
COMPUTING
2004
204views more  COMPUTING 2004»
13 years 6 months ago
Image Registration by a Regularized Gradient Flow. A Streaming Implementation in DX9 Graphics Hardware
The presented image registration method uses a regularized gradient flow to correlate the intensities in two images. Thereby, an energy functional is successively minimized by des...
Robert Strzodka, Marc Droske, Martin Rumpf
GECCO
2007
Springer
207views Optimization» more  GECCO 2007»
14 years 26 days ago
A data parallel approach to genetic programming using programmable graphics hardware
In recent years the computing power of graphics cards has increased significantly. Indeed, the growth in the computing power of these graphics cards is now several orders of magn...
Darren M. Chitty
ISCAS
2007
IEEE
161views Hardware» more  ISCAS 2007»
14 years 1 months ago
Hardware Architecture of a Parallel Pattern Matching Engine
Abstract— Several network security and QoS applications require detecting multiple string matches in the packet payload by comparing it against predefined pattern set. This proc...
Meeta Yadav, Ashwini Venkatachaliah, Paul D. Franz...