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IPPS
1999
IEEE
13 years 11 months ago
Solving Satisfiability Problems on FPGAs using Experimental Unit Propagation Heuristic
This paperpresents new resultson anapproach for solvingsatisfiability problems (SAT), that is, creating a logic circuit that is specialized to solve each problem instance on Field ...
Takayuki Suyama, Makoto Yokoo, Akira Nagoya
AHS
2006
IEEE
142views Hardware» more  AHS 2006»
14 years 1 months ago
On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition
To increase the flexibility of single-chip evolvable hardware systems, we explore possibilities of systems with the evolutionary algorithm implemented in software on an onchip pr...
Kyrre Glette, Jim Torresen, Moritoshi Yasunaga, Yo...
IPPS
2010
IEEE
13 years 5 months ago
Adapting cache partitioning algorithms to pseudo-LRU replacement policies
Abstract-- Recent studies have shown that cache partitioning is an efficient technique to improve throughput, fairness and Quality of Service (QoS) in CMP processors. The cache par...
Kamil Kedzierski, Miquel Moretó, Francisco ...
CODES
2003
IEEE
14 years 21 days ago
A fast parallel reed-solomon decoder on a reconfigurable architecture
This paper presents a software implementation of a very fast parallel Reed-Solomon decoder on the second generation of MorphoSys reconfigurable computation platform, which is targ...
Arezou Koohi, Nader Bagherzadeh, Chengzi Pan
EWC
2006
61views more  EWC 2006»
13 years 7 months ago
Embarrassingly parallel mesh refinement by edge subdivision
We have previously proposed a new technique for the communication-free adaptive refinement of tetrahedral meshes that works for all configurations. Implementations of the scheme mu...
David C. Thompson, Philippe P. Pébay