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ASAP
2005
IEEE
135views Hardware» more  ASAP 2005»
14 years 1 months ago
Via-Aware Global Routing for Good VLSI Manufacturability and High Yield
CAD tools have become more and more important for integrated circuit (IC) design since a complicated system can be designed into a single chip, called system-on-a-chip (SOC), in w...
Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu...
VLSI
2010
Springer
13 years 2 months ago
A design workflow for dynamically reconfigurable multi-FPGA systems
Multi-FPGA systems (MFS's) represent a promising technology for various applications, such as the implementation of supercomputers and parallel and computational intensive emu...
Alessandro Panella, Marco D. Santambrogio, Frances...
ICCAD
2003
IEEE
132views Hardware» more  ICCAD 2003»
14 years 4 months ago
A Sum-over-Paths Impulse-Response Moment-Extraction Algorithm for IC-Interconnect Networks: Verification, Coupled RC Lines
We have created a stochastic impulse-response (IR) momentextraction algorithm for RC circuit networks. It employs a newly discovered Feynman Sum-over-Paths Postulate. Full paralle...
Yannick L. Le Coz, Dhivya Krishna, Dusan M. Petran...
VLSID
2009
IEEE
150views VLSI» more  VLSID 2009»
14 years 8 months ago
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis
We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully ...
Alejandro Czutro, Ilia Polian, Matthew D. T. Lewis...
IPPS
1997
IEEE
13 years 11 months ago
Parallel Simulated Annealing: An Adaptive Approach
This paper analyses alternatives for the parallelization of the Simulated Annealing algorithm when applied to the placement of modules in a VLSI circuit considering the use of PVM...
Jonas Knopman, Júlio S. Aude