284 search results - page 10 / 57 » Parallel buffers for chip multiprocessors |
144
Voted
IEEEPACT
2005
IEEE
15 years 9 months ago
2005
IEEE
Transactional Coherence and Consistency (TCC) is a novel coherence scheme for shared memory multiprocessors that uses programmer-defined transactions as the fundamental unit of p...
119
Voted
IEEEPACT
2009
IEEE
15 years 1 months ago
2009
IEEE
Abstract--The centralized structures necessary for the extraction of instruction-level parallelism (ILP) are consuming progressively smaller portions of the total die area of chip ...
122
Voted
ISCAS
2007
IEEE
15 years 10 months ago
2007
IEEE
— This paper presents performance and area evaluation of a homogeneous multiprocessor communication system based on network-on-chip (NoC) in FPGA platforms. Two homogenous chip m...
142
Voted
ASPLOS
1998
ACM
15 years 8 months ago
1998
ACM
Thread-level speculation is a technique that enables parallel execution of sequential applications on a multiprocessor. This paper describes the complete implementation of the sup...
130
Voted
HPCC
2005
Springer
15 years 9 months ago
2005
Springer
In this paper we present an exhaustive evaluation of the memory subsystem in a chip-multiprocessor (CMP) architecture composed of 16 cores. The characterization is performed making...