360 search results - page 17 / 72 » Parallel processing flow models on desktop hardware |
FCCM
2006
IEEE
14 years 2 months ago
2006
IEEE
Abstract— This paper introduces a novel architecture for performing the core computations required by dynamic programming (DP) techniques. The latter pertain to a vast range of a...
DAC
1997
ACM
14 years 23 days ago
1997
ACM
A methodology for architecture exploration of look-up table based decoders is presented. For the degree of parallel processing a trade-off can be made by exploring system level an...
3DPVT
2006
IEEE
14 years 2 months ago
2006
IEEE
In this work we propose a scanline optimization procedure for computational stereo using a linear smoothness cost model performed by programmable graphics hardware. The main idea ...
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
DSP applications can be suitably represented using Process Network Models. This paper uses a modification of Kahn Process Network to solve the problem of finding an optimum arch...
ICASSP
2011
IEEE
13 years 10 days ago
2011
IEEE
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...