360 search results - page 18 / 72 » Parallel processing flow models on desktop hardware |
ICECCS
1995
IEEE
14 years 4 days ago
1995
IEEE
When trying to describe the behaviour of large systems, such as the business processes of large enterprises, we often adopt diagramming techniques based on derivatives of data flo...
TVLSI
2008
13 years 8 months ago
2008
This paper describes a reconfigurable architecture based on field-programmable gate-array (FPGA) technology for monitoring and analyzing network traffic at increasingly high networ...
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
This paper addresses the problem of stochastic task execution time estimation agnostic to the process distributions. The proposed method is orthogonal to the application structure ...
ICS
2005
Tsinghua U.
14 years 2 months ago
2005
Tsinghua U.
As parallel jobs get bigger in size and finer in granularity, “system noise” is increasingly becoming a problem. In fact, fine-grained jobs on clusters with thousands of SMP...
CATA
2010
13 years 8 months ago
2010
In this paper, a hardware implementation of the AES128 encryption algorithm is proposed. A unique feature of the proposed pipelined design is that the round keys, which are consum...