360 search results - page 36 / 72 » Parallel processing flow models on desktop hardware |
ICS
2009
Tsinghua U.
14 years 3 months ago
2009
Tsinghua U.
In this work, we propose a new FPGA design flow that combines the CUDA programming model from Nvidia with the state of the art high-level synthesis tool AutoPilot from AutoESL, to...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper addresses the allocation of link capacities in the automated design process of a network-on-chip based system. Communication resource costs are minimized under Quality-...
CSE
2011
IEEE
12 years 8 months ago
2011
IEEE
— In network based applications, packet capture is the main area that attracts many researchers in developing traffic monitoring systems. Along with the packet capture, many othe...
IPPS
2005
IEEE
14 years 2 months ago
2005
IEEE
Parallel random access memory, or PRAM, is a now venerable model of parallel computation that that still retains its usefulness for the design and analysis of parallel algorithms....
CODES
2003
IEEE
14 years 1 months ago
2003
IEEE
We present an approach to the automatic derivation of executable Process Network specifications from Weakly Dynamic Applications. We introduce the notions of Dynamic Single Assig...