Sciweavers

360 search results - page 42 / 72
» Parallel processing flow models on desktop hardware
Sort
View
IPPS
1994
IEEE
14 years 23 days ago
Building Multithreaded Architectures with Off-the-Shelf Microprocessors
Present-day parallel computers often face the problems of large software Overheadsfor process switching and interprocessor communication. These problems are addressed by the Multi...
Herbert H. J. Hum, Kevin B. Theobald, Guang R. Gao
CF
2009
ACM
14 years 3 months ago
Wave field synthesis for 3D audio: architectural prospectives
In this paper, we compare the architectural perspectives of the Wave Field Synthesis (WFS) 3D-audio algorithm mapped on three different platforms: a General Purpose Processor (GP...
Dimitris Theodoropoulos, Catalin Bogdan Ciobanu, G...
IPPS
2006
IEEE
14 years 2 months ago
FPGA implementation of a license plate recognition SoC using automatically generated streaming accelerators
Modern FPGA platforms provide the hardware and software infrastructure for building a bus-based System on Chip (SoC) that meet the applications requirements. The designer can cust...
Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan L...
XSYM
2009
Springer
139views Database» more  XSYM 2009»
14 years 3 months ago
A Data Parallel Algorithm for XML DOM Parsing
Abstract. The extensible markup language XML has become the de facto standard for information representation and interchange on the Internet. XML parsing is a core operation perfor...
Bhavik Shah, Praveen Rao, Bongki Moon, Mohan Rajag...
BMCBI
2005
246views more  BMCBI 2005»
13 years 8 months ago
ParPEST: a pipeline for EST data analysis based on parallel computing
Background: Expressed Sequence Tags (ESTs) are short and error-prone DNA sequences generated from the 5' and 3' ends of randomly selected cDNA clones. They provide an im...
Nunzio D'Agostino, Mario Aversano, Maria Luisa Chi...