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» Parallel simulation of chip-multiprocessor architectures
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HPCA
2008
IEEE
14 years 8 months ago
Roughness of microarchitectural design topologies and its implications for optimization
Recent advances in statistical inference and machine learning close the divide between simulation and classical optimization, thereby enabling more rigorous and robust microarchit...
Benjamin C. Lee, David M. Brooks
HPCA
2003
IEEE
14 years 8 months ago
Caches and Hash Trees for Efficient Memory Integrity
We study the hardware cost of implementing hash-tree based verification of untrusted external memory by a high performance processor. This verification could enable applications s...
Blaise Gassend, G. Edward Suh, Dwaine E. Clarke, M...
CLUSTER
2008
IEEE
14 years 3 months ago
Supporting storage resources in Urgent Computing Environments
Abstract—The Special PRiority and Urgent Computing Environment (SPRUCE) provides on-demand access to highperformance computing resources for time-critical applications. While SPR...
Jason Cope, Henry M. Tufo
ISCAS
2007
IEEE
114views Hardware» more  ISCAS 2007»
14 years 2 months ago
On the Compensation of Magnitude Response Mismatches in M-channel Time-interleaved ADCs
Abstract— Parallel time-interleaved analog-to-digital converters (TIADCs) are an attractive architecture to realize low-power and high-speed data conversion. As a drawback of suc...
Stefan Mendel, Christian Vogel
GCC
2004
Springer
14 years 1 months ago
Trust Establishment in Large Scale Grid Settings
Trust establishment is hard in grid architecture by the ad hoc nature. To set up trust in large scale of network is more difficult. In this paper, we propose an automatic key manag...
Bo Zhu, Tieyan Li, Huafei Zhu, Mohan S. Kankanhall...