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» Parallel simulation of chip-multiprocessor architectures
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DPHOTO
2009
116views Hardware» more  DPHOTO 2009»
13 years 6 months ago
Interleaved imaging: an imaging system design inspired by rod-cone vision
Under low illumination conditions, such as moonlight, there simply are not enough photons present to create a high quality color image with integration times that avoid camera-sha...
Manu Parmar, Brian A. Wandell
MICRO
2003
IEEE
125views Hardware» more  MICRO 2003»
14 years 1 months ago
WaveScalar
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...
Steven Swanson, Ken Michelson, Andrew Schwerin, Ma...
EGH
2009
Springer
13 years 6 months ago
Efficient ray traced soft shadows using multi-frusta tracing
Ray tracing has long been considered to be superior to rasterization because its ability to trace arbitrary rays, allowing it to simulate virtually any physical light transport ef...
Carsten Benthin, Ingo Wald
EGH
2004
Springer
14 years 1 months ago
A programmable vertex shader with fixed-point SIMD datapath for low power wireless applications
The real time 3D graphics becomes one of the attractive applications for 3G wireless terminals although their battery lifetime and memory bandwidth limit the system resources for ...
Ju-Ho Sohn, Ramchan Woo, Hoi-Jun Yoo
DATE
2010
IEEE
113views Hardware» more  DATE 2010»
14 years 1 months ago
PM-COSYN: PE and memory co-synthesis for MPSoCs
—Multi-Processor System-on-Chips (MPSoCs) exploit task-level parallelism to achieve high computation throughput, but concurrent memory accesses from multiple PEs may cause memory...
Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang