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» Parallel simulation of chip-multiprocessor architectures
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HPCA
2009
IEEE
14 years 9 months ago
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
Andrew DeOrio, Ilya Wagner, Valeria Bertacco
HPCA
2009
IEEE
14 years 9 months ago
In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects
Realizing scalable cache coherence in the many-core era comes with a whole new set of constraints and opportunities. It is widely believed that multi-hop, unordered on-chip networ...
Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha
HPCA
2008
IEEE
14 years 8 months ago
Regional congestion awareness for load balance in networks-on-chip
Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiprocessors and system-on-chip designs. Existing interconnection networks use...
Paul Gratz, Boris Grot, Stephen W. Keckler
CASES
2006
ACM
14 years 2 months ago
High-level power analysis for multi-core chips
Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs...
Noel Eisley, Vassos Soteriou, Li-Shiuan Peh
MOBICOM
2009
ACM
14 years 3 months ago
A scalable micro wireless interconnect structure for CMPs
This paper describes an unconventional way to apply wireless networking in emerging technologies. It makes the case for using a two-tier hybrid wireless/wired architecture to inte...
Suk-Bok Lee, Sai-Wang Tam, Ioannis Pefkianakis, So...