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» Parallel simulation of chip-multiprocessor architectures
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DATE
2006
IEEE
99views Hardware» more  DATE 2006»
14 years 2 months ago
Parallel co-simulation using virtual synchronization with redundant host execution
In traditional parallel co-simulation approaches, the simulation speed is heavily limited by time synchronization overhead between simulators and idle time caused by data dependen...
Dohyung Kim, Soonhoi Ha, Rajesh Gupta
MICRO
2007
IEEE
108views Hardware» more  MICRO 2007»
14 years 2 months ago
FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators
This paper describes FAST, a novel simulation methodology that can produce simulators that (i) are orders of magnitude faster than comparable simulators, (ii) are cycleaccurate, (...
Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Pa...
HPCA
1999
IEEE
14 years 24 days ago
Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors
Previous simulators for shared-memory architectures have imposed a large tradeoff between simulation accuracy and speed. Most such simulators model simple processors that do not e...
Murthy Durbhakula, Vijay S. Pai, Sarita V. Adve
FCCM
2005
IEEE
124views VLSI» more  FCCM 2005»
14 years 2 months ago
Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA
The CLA-EC is a model obtained by combining the concepts of cellular learning automata and evolutionary algorithms. The parallel structure of the CLA-EC makes it suitable for hard...
Arash Hariri, Reza Rastegar, Morteza Saheb Zamani,...
ICCSA
2004
Springer
14 years 1 months ago
Publishing and Executing Parallel Legacy Code Using an OGSI Grid Service
Abstract. This paper describes an architecture for publishing and executing parallel legacy code using an OGSI Grid service. A framework is presented that aids existing legacy appl...
Thierry Delaitre, Ariel Goyeneche, Tamás Ki...