770 search results - page 5 / 154 » Parallel simulation of chip-multiprocessor architectures |
ICS
2001
Tsinghua U.
13 years 11 months ago
2001
Tsinghua U.
Recent proposals for Chip Multiprocessors (CMPs) advocate speculative, or implicit, threading in which the hardware employs prediction to peel off instruction sequences (i.e., imp...
PDP
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Execution of applications on upcoming highperformance computing (HPC) systems introduces a variety of new challenges and amplifies many existing ones. These systems will...
EUROPAR
1997
Springer
13 years 11 months ago
1997
Springer
The shared cache structures and snoop cache structures for single-chip multiprocessors are evaluated and compared using an instruction level simulator. Simulation results show that...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
IISWC
2006
IEEE
14 years 1 months ago
2006
IEEE
— As CMPs are emerging as the dominant architecture for a wide range of platforms (from embedded systems and game consoles, to PCs, and to servers) the need to manage on-chip res...