Sciweavers

8125 search results - page 1595 / 1625
» Parallelism and evolutionary algorithms
Sort
View
HPCA
2009
IEEE
14 years 10 months ago
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
Andrew DeOrio, Ilya Wagner, Valeria Bertacco
HPCA
2009
IEEE
14 years 10 months ago
Blueshift: Designing processors for timing speculation from the ground up
Several recent processor designs have proposed to enhance performance by increasing the clock frequency to the point where timing faults occur, and by adding error-correcting supp...
Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey ...
HPCA
2009
IEEE
14 years 10 months ago
Fast complete memory consistency verification
The verification of an execution against memory consistency is known to be NP-hard. This paper proposes a novel fast memory consistency verification method by identifying a new na...
Yunji Chen, Yi Lv, Weiwu Hu, Tianshi Chen, Haihua ...
KDD
2009
ACM
187views Data Mining» more  KDD 2009»
14 years 10 months ago
New ensemble methods for evolving data streams
Advanced analysis of data streams is quickly becoming a key area of data mining research as the number of applications demanding such processing increases. Online mining when such...
Albert Bifet, Bernhard Pfahringer, Geoffrey Holmes...
HPCA
2008
IEEE
14 years 10 months ago
Regional congestion awareness for load balance in networks-on-chip
Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiprocessors and system-on-chip designs. Existing interconnection networks use...
Paul Gratz, Boris Grot, Stephen W. Keckler
« Prev « First page 1595 / 1625 Last » Next »