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CODES
2005
IEEE
14 years 1 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
ESA
1998
Springer
162views Algorithms» more  ESA 1998»
13 years 11 months ago
External Memory Algorithms
Abstract. Data sets in large applications are often too massive to t completely inside the computer's internal memory. The resulting input output communication or I O between ...
Jeffrey Scott Vitter
ICPP
2008
IEEE
14 years 1 months ago
A Replication Overlay Assisted Resource Discovery Service for Federated Systems
Abstract—Federated systems have recently attracted much attention because they allow loosely coupled organizations to share resources for common benefits. However, discovering r...
Hao Yang, Fan Ye, Zhen Liu
SIAMCOMP
2000
118views more  SIAMCOMP 2000»
13 years 7 months ago
Constructive, Deterministic Implementation of Shared Memory on Meshes
This paper describes a scheme to implement a shared address space of size m on an n-node mesh, with m polynomial in n, where each mesh node hosts a processor and a memory module. A...
Andrea Pietracaprina, Geppino Pucci, Jop F. Sibeyn
ICDCS
2003
IEEE
14 years 24 days ago
Protecting BGP Routes to Top Level DNS Servers
—The Domain Name System (DNS) is an essential part of the Internet infrastructure and provides fundamental services, such as translating host names into IP addresses for Internet...
Lan Wang, Xiaoliang Zhao, Dan Pei, Randy Bush, Dan...