3 search results - page 1 / 1 » Parallelism-Aware Batch Scheduling: Enhancing both Performan... |
153
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ISCA
2008
IEEE
16 years 16 days ago
2008
IEEE
In a chip-multiprocessor (CMP) system, the DRAM system is shared among cores. In a shared DRAM system, requests from a thread can not only delay requests from other threads by cau...
192
Voted
ISCA
2011
IEEE
14 years 9 months ago
2011
IEEE
Chip multiprocessors (CMPs) share a large portion of the memory subsystem among multiple cores. Recent proposals have addressed high-performance and fair management of these share...
219
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INFOCOM
1998
IEEE
15 years 10 months ago
1998
IEEE
To support the Internet's explosive growth and expansion into a true integrated services network, there is a need for cost-effective switching technologies that can simultaneo...