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TVLSI
2010
13 years 2 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...
ISCA
2011
IEEE
287views Hardware» more  ISCA 2011»
12 years 11 months ago
Scalable power control for many-core architectures running multi-threaded applications
Optimizing the performance of a multi-core microprocessor within a power budget has recently received a lot of attention. However, most existing solutions are centralized and cann...
Kai Ma, Xue Li, Ming Chen, Xiaorui Wang
ICLP
2011
Springer
12 years 10 months ago
Transaction Logic with Defaults and Argumentation Theories
Transaction Logic is an extension of classical logic that gracefully integrates both declarative and procedural knowledge and has proved itself as a powerful formalism for many ad...
Paul Fodor, Michael Kifer
PPL
2011
12 years 10 months ago
Mpi on millions of Cores
Petascale parallel computers with more than a million processing cores are expected to be available in a couple of years. Although MPI is the dominant programming interface today ...
Pavan Balaji, Darius Buntinas, David Goodell, Will...
CVPR
2012
IEEE
11 years 9 months ago
Recovering free space of indoor scenes from a single image
In this paper we consider the problem of recovering the free space of an indoor scene from its single image. We show that exploiting the box like geometric structure of furniture ...
Varsha Hedau, Derek Hoiem, David A. Forsyth
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