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CASES
2004
ACM
14 years 1 months ago
Procedure placement using temporal-ordering information: dealing with code size expansion
Abstract— In a direct-mapped instruction cache, all instructions that have the same memory address modulo the cache size, share a common and unique cache slot. Instruction cache ...
Christophe Guillon, Fabrice Rastello, Thierry Bida...
CF
2010
ACM
14 years 1 months ago
Interval-based models for run-time DVFS orchestration in superscalar processors
We develop two simple interval-based models for dynamic superscalar processors. These models allow us to: i) predict with great accuracy performance and power consumption under va...
Georgios Keramidas, Vasileios Spiliopoulos, Stefan...
DATE
1999
IEEE
172views Hardware» more  DATE 1999»
14 years 13 days ago
An Object-Based Executable Model for Simulation of Real-Time Hw/Sw Systems
This paper describes a simulation technique for RealTime Hw/Sw systems based on an object executable model. It allows designers to seamlessly estimate and verify their solutions f...
Olivier Pasquier, Jean Paul Calvez
IPCCC
1999
IEEE
14 years 12 days ago
Accurately modeling speculative instruction fetching in trace-driven simulation
Performance evaluation of modern, highly speculative, out-of-order microprocessors and the corresponding production of detailed, valid, accurate results have become serious challe...
R. Bhargava, L. K. John, F. Matus
CSCW
1998
ACM
14 years 10 days ago
Sustaining Mentoring Relationships On-Line
we have documented shares some of the influences discussed by Ackerman et. al., but has unique dynamics of its own which present unique technical and social demands. Using several ...
D. Kevin O'Neill, Louis M. Gomez
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