7092 search results - page 1289 / 1419 » Parallelizing constraint programs |
CASES
2004
ACM
15 years 7 months ago
2004
ACM
Abstract— In a direct-mapped instruction cache, all instructions that have the same memory address modulo the cache size, share a common and unique cache slot. Instruction cache ...
122
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CF
2010
ACM
15 years 7 months ago
2010
ACM
We develop two simple interval-based models for dynamic superscalar processors. These models allow us to: i) predict with great accuracy performance and power consumption under va...
133
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DATE
1999
IEEE
15 years 6 months ago
1999
IEEE
This paper describes a simulation technique for RealTime Hw/Sw systems based on an object executable model. It allows designers to seamlessly estimate and verify their solutions f...
139
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IPCCC
1999
IEEE
15 years 6 months ago
1999
IEEE
Performance evaluation of modern, highly speculative, out-of-order microprocessors and the corresponding production of detailed, valid, accurate results have become serious challe...
CSCW
1998
ACM
15 years 6 months ago
1998
ACM
we have documented shares some of the influences discussed by Ackerman et. al., but has unique dynamics of its own which present unique technical and social demands. Using several ...