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FCCM
2008
IEEE
165views VLSI» more  FCCM 2008»
14 years 2 months ago
Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing
High-Level Languages (HLLs) for FPGAs (FieldProgrammable Gate Arrays) facilitate the use of reconfigurable computing resources for application developers by using familiar, higher...
John Curreri, Seth Koehler, Brian Holland, Alan D....
IEEEPACT
2008
IEEE
14 years 2 months ago
The PARSEC benchmark suite: characterization and architectural implications
This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs). Prev...
Christian Bienia, Sanjeev Kumar, Jaswinder Pal Sin...
ISCAS
2008
IEEE
106views Hardware» more  ISCAS 2008»
14 years 2 months ago
Hilbert transformers with a piecewise-polynomial-sinusoidal impulse response
— Hilbert transformers are one of the very important special classes of finite impulse response (FIR) filters used in signal processing applications. A method is presented to s...
Raija Lehto, Tapio Saramäki, Olli Vainio
ISORC
2008
IEEE
14 years 2 months ago
A Real-Time Java Component Model
The Real-Time Specification for Java (RTSJ) [10] is becoming a popular choice in the world of real-time programming. However, the complexities introduced by RTSJ bring the needs ...
Ales Plsek, Philippe Merle, Lionel Seinturier
SBACPAD
2008
IEEE
170views Hardware» more  SBACPAD 2008»
14 years 2 months ago
Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
James Poe, Chang-Burm Cho, Tao Li
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