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ISCAS
2007
IEEE
161views Hardware» more  ISCAS 2007»
14 years 3 months ago
Hardware Architecture of a Parallel Pattern Matching Engine
Abstract— Several network security and QoS applications require detecting multiple string matches in the packet payload by comparing it against predefined pattern set. This proc...
Meeta Yadav, Ashwini Venkatachaliah, Paul D. Franz...
CF
2010
ACM
14 years 2 months ago
Variant-based competitive parallel execution of sequential programs
Competitive parallel execution (CPE) is a simple yet attractive technique to improve the performance of sequential programs on multi-core and multi-processor systems. A sequential...
Oliver Trachsel, Thomas R. Gross
ICANN
2001
Springer
14 years 1 months ago
A Computational Intelligence Approach to Optimization with Unknown Objective Functions
In many practical engineering design problems, the form of objective function is not given explicitly in terms of design variables. Given the value of design variables, under this ...
Hirotaka Nakayama, Masao Arakawa, Rie Sasaki
CLUSTER
2008
IEEE
14 years 3 months ago
Divisible load scheduling with improved asymptotic optimality
—Divisible load model allows scheduling algorithms that give nearly optimal makespan with practical computational complexity. Beaumont et al. have shown that their algorithm prod...
Reiji Suda
3DPVT
2006
IEEE
233views Visualization» more  3DPVT 2006»
14 years 3 months ago
Scanline Optimization for Stereo on Graphics Hardware
In this work we propose a scanline optimization procedure for computational stereo using a linear smoothness cost model performed by programmable graphics hardware. The main idea ...
Christopher Zach, Mario Sormann, Konrad F. Karner