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VLSISP
2002
112views more  VLSISP 2002»
13 years 8 months ago
Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks
Large-grain synchronous dataflow graphs or multi-rate graphs have the distinct feature that the nodes of the dataflow graph fire at different rates. Such multi-rate large-grain dat...
Ramaswamy Govindarajan, Guang R. Gao, Palash Desai
ISCAS
2005
IEEE
133views Hardware» more  ISCAS 2005»
14 years 2 months ago
Multiobjective VLSI cell placement using distributed simulated evolution algorithm
— Simulated Evolution (SimE) is a sound stochastic approximation algorithm based on the principles of adaptation. If properly engineered it is possible for SimE to reach nearopti...
Sadiq M. Sait, Ali Mustafa Zaidi, Mustafa I. Ali
IPPS
2002
IEEE
14 years 2 months ago
A High Performance Algorithm for Incompressible Flows Using Local Solenoidal Functions
The convergence of iterative methods used to solve the linear systems arising in incompressible flow problems is sensitive to flow parameters such as the Reynolds number, time s...
Sreekanth R. Sambavaram, Vivek Sarin
CORR
2011
Springer
197views Education» more  CORR 2011»
13 years 4 months ago
High-Throughput Transaction Executions on Graphics Processors
OLTP (On-Line Transaction Processing) is an important business system sector in various traditional and emerging online services. Due to the increasing number of users, OLTP syste...
Bingsheng He, Jeffrey Xu Yu
HPCA
2002
IEEE
14 years 9 months ago
Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requir...
Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T....