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HPCA
2009
IEEE
14 years 9 months ago
iCFP: Tolerating all-level cache misses in in-order processors
Growing concerns about power have revived interest in in-order pipelines. In-order pipelines sacrifice single-thread performance. Specifically, they do not allow execution to flow...
Andrew D. Hilton, Santosh Nagarakatte, Amir Roth
HPCA
2008
IEEE
14 years 9 months ago
EXCES: External caching in energy saving storage systems
Power consumption within the disk-based storage subsystem forms a substantial portion of the overall energy footprint in commodity systems. Researchers have proposed external cach...
Luis Useche, Jorge Guerra, Medha Bhadkamkar, Mauri...
HPCA
2005
IEEE
14 years 9 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob
HPCA
2004
IEEE
14 years 9 months ago
Accurate and Complexity-Effective Spatial Pattern Prediction
Recent research suggests that there are large variations in a cache's spatial usage, both within and across programs. Unfortunately, conventional caches typically employ fixe...
Chi F. Chen, Se-Hyun Yang, Babak Falsafi, Andreas ...
PODS
2005
ACM
164views Database» more  PODS 2005»
14 years 9 months ago
Lower bounds for sorting with few random accesses to external memory
We consider a scenario where we want to query a large dataset that is stored in external memory and does not fit into main memory. The most constrained resources in such a situati...
Martin Grohe, Nicole Schweikardt
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